[SatNews] Adding to its line of Soft Decision Forward Error Correction (FEC) cores for…
…100/200G optical communications, ViaSat Inc. (Nasdaq:VSAT) is shipping a Multichannel AES-256/128 bit Security IP Core. The core consists of a comprehensive set of pre-integrated security functions that customers can implement into FPGA or ASIC designs. More than just an “AES algorithm,” the multichannel engine is a complete security system core. The security core requires only a one-time configuration load after power-cycle/reset. Once configured, the security core will automatically set up a secure connection to its peer core(s) in the distant-end equipment. The management interface also provides status information to the host, indicating the status of security connection(s) as well as other link statistics. Key specifications for the security core:
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• 100 Gbps data interface
• Single byte per frame overhead
• Built-in, non-deterministic, random number generator generates Traffic Encryption Keys (TEKs)
• Automatic key-roller and TEK generation
• Controlled cryptographic bypass for non-encrypted frame data
The core is implemented in a Xilinx Virtex®-6 FPGA with less than 38 percent use of available resources.
