[SatNews] Stellamar, a leading provider of analog replacement IP solutions for microelectronics customers, has announced…
…first pass silicon validation success of its All Digital ADC technology. The project was completed for SEAKR Engineering, a provider of advanced state-of-the-art electronic avionics for space applications. Stellamar All Digital ADC technology was fabricated on Honeywell HX-5 150nm Structured Array process.
The All Digital ADC technology performs analog to digital conversion for many different sensor applications. In contrast to most analog to digital converters, All Digital ADC IP is designed using all digital library cells and removes the need for cumbersome analog circuitry. These differences allow All Digital ADC IP to leverage all the benefits of digital design including smaller area, lower power and the use of radiation hard processes without any special design or processing steps.
Beyond these benefits, All Digital ADC IP simplifies design and test, increases reliability for critical applications, and saves programs significant money by removing external parts. “We are extremely happy to announce silicon success in conjunction with our partners,” said Allan Chin, CEO of Stellamar. “A lot of hard work went into the development of the technology, and it is great to see all of that labor help make a customer’s project successful.”
“SEAKR uses the Stellamar ADC as a cost effect means to monitor the temperature diode of a high performance microprocessor used in a spacecraft application. Integrating the ADC into our ASIC allowed us to avoid adding a costly radiation hardened ADC to the board for this function,” said Jeff Pritchard, CTO of SEAKR. “The ADC effectively lets the microprocessor monitor its own temperature, shed loading, and alert the spacecraft if an over temperature condition has occurred. The Stellamar ADC also saved us pins on the ASIC, which was highly pin constrained. The Stellamar folks were great to work with, and provided top-notch support during the integrating and testing phases of the design.”
